1. Field of the Invention
The present invention relates to a shared buffer memory switch for an ATM (Asynchronous Transfer Mode) switching system and its broadcasting control method, and, more particularly, to a shared buffer memory switch which can output ordinary cells and broadcasting cells in the order of their arrival without providing a specific address pointer queue for a broadcasting control and its broadcasting control method.
2. Description of the Related Art
Buffer memories are generally used for a switch of the ATM switching system. This is mainly for the purpose of avoiding a collision of cells (each cell forms a packet of information of fixed length) in the switch in which cells to be switched are flowing. There are several switch architectures for the ATM switching system, and they are categorized as the following four types of switches in the view point of the location of buffer memories being provided in the switch, and each of architecture is shown in FIG. 1.
The first type of switch is a shared buffer memory switch, which has a buffer memory commonly used for all input traffic (the flow of cells coming into the switch through input ports) to be routed to any output port. The second type of switch is an input buffer memory switch, which has an input buffer memory provided at each of input ports of the switching matrix for adjusting an output of each cell into an output highway of the switch to avoid a collision of cells in the highway. The third type of switch is an input and output buffer switch, which has an input buffer memory and an output buffer memory being provided at each of input ports and output ports of the switch respectively, and the transmission speed of cells in the switch is accelerated for avoiding a collision of cells. The fourth type of switch is a crosspoint buffer switch, which has a buffer memory provided at each of the crosspoints of the switching matrix.
Among those four types of switch, the shared buffer memory switch is explained below by referring to FIG. 2 which illustrates a block diagram showing an N.times.N (a number of input ports and output ports is N respectively) shared buffer memory switch, and other related drawings of FIGS. 3, 4, 5 and 6.
As shown in FIG. 2, the shared buffer memory switch has the following functional components;
a shared buffer memory 3 with a large capacity for temporarily storing cells from any of the input ports 11 to any of output ports 14, PA1 a cell multiplexer 1 for multiplexing incoming cells through input ports and outputting the multiplexed cells to a time division multiplex data bus 12, and a cell demultiplexer 7 for demultiplexing and distributing the multiplexed cells on the time division multiplex data bus 12 to each of output ports, PA1 a shared buffer memory control 2 for controlling the operation of writing cells on the time division multiplex data bus 12 into the shared buffer memory 3 in a writing cycle of the operation, and reading cells in the shared buffer memory 3 out to the time division multiplex data bus 12 in a reading cycle of the operation, PA1 a FIFO (first-in-first-out) memory 4 has an address pointer queue for storing and indicating address information of idle area which is available in the shared buffer memory 3, PA1 a FIFO memory 5, which is one physical memory divided into several logical queuing memories, has address pointer queues for each of output ports (from No. 1 to No. N) and for a broadcasting operation, by which one cell from an input port is transmitted to a plural number of output ports simultaneously, and each address pointer queue stores and indicates the address information of the shared buffer memory 3 in which the cell to be routed to the output port is stored, simultaneous access to multiple address pointer queues not being available as this memory is a single physical memory, and PA1 a broadcast registration table 6 for the broadcasting operation and storing the information of broadcasting destinations in the form of bit map data corresponding to each of output ports.
FIG. 3 shows an outline of cell format used for the ATM switching system. Each cell has a header field of 5 bytes and a user information field of 48 bytes, and the header field contains various information for handling this cell for call processing control. Among those information, VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier) are used as routing information, and are extracted by the cell multiplexer 1. This routing information extracted by the cell multiplexer is supplied to the shared buffer memory control 2 through a routing information path 13.
The cell multiplexer 1 also multiplexes all cells coming into the switch through each of input ports, and outputs them in a form of frame on the time division multiplex data bus 12 as shown in FIG. 4.
FIG. 4 illustrates a multiframe format on the time division multiplex data bus 12. As shown in this figure, a multiframe 21 is consisted by a cell slot group 22 for cells coming into through the input ports 11 and a cell slot group 23 for cells going out through the output ports 14. Each cell slot in each cell slot group is assigned in correspondence to each input port and each output port, e.g. the cell slot 24 is assigned to a cell from input port No. 1 and the cell slot 25 is assigned to a cell to output port No. 1. FIG. 4 also illustrates a routing information on the routing information path 13. The routing information extracted by the cell multiplexer 1 is put into each slot position which corresponds to each input port, e.g. the slot position 26 contains the routing information for the cell from the input port No. 1.
FIGS. 5(a), (b), (c) and (d) are provided for explaining how the shared buffer memory switch works for switching ordinary cells.
As shown in FIG. 5(a), the cell multiplexer 1 multiplexes all cells coming through input ports 11 and puts each of those cells into each cell slot position for the input port frame on the time division multiplex data bus 12 in correspondence to each input port, and at the same time, the routing information extracted from the header of each cell is transferred through the routing information path 13. The routing information indicates the number of outgoing port for the cell to be routed. As an example, FIG. 5(a) shows No. 3 outgoing port as the routing information for the cell coming through No. 1 input port and No. 7 outgoing port as the routing information for the cell coming through No. N input port.
FIG. 5(b) illustrates the writing operation by the shared buffer memory control 2. It is assumed that the idle area of shared buffer memory 3 exists in each address of "BBB", "MMM" and "NNN" (other idle areas between the address "BBB" and the address "MMM" are omitted). The address information of those idle area are stored in the address pointer queue of FIFO 4 through the information path 15.
When the shared buffer memory control 2 receives the routing information corresponding to the No. 1 input port from the cell multiplexer 1 through the routing information path 13, it discriminates the number of outgoing port for the cell to be routed and also it extracts an idle address of the shared buffer memory 3 from the address pointer queue of FIFO 4 through the information path 16 for storing this cell into the shared buffer memory 3. In this example shown in FIG. 5(b), the routing destination of the cell from No. 1 input port is to No. 3 output port, and the address "BBB" is extracted for storing the cell being transferred in the cell slot for No. 1 input port on the time division multiplex data bus 12 into the shared buffer memory 3.
Having completed the storage of the cell into the address "BBB" of the shared buffer memory 3, the shared buffer memory control 2 then writes the address information of "BBB" into the address pointer queue of FIFO 5 corresponding to the No. 3 outgoing port through the information path 17.
In this manner, the cell in the cell slot for No. N input port on the time division multiplex data bus 12 is stored in the shared buffer memory with its address of "MMM", and the address information of "MMM" is written in the address pointer queue of FIFO 5 for the No. 7 outgoing port.
The reading cycle of operation for the shared buffer memory control 2 will be described hereafter by referring to FIG. 5(c).
In the reading cycle, the shared buffer memory control 2 reads the address pointer queue of FIFO 5 for each output port one by one through the information path 18. The address information read out from the address pointer queue of FIFO 5 for a specific outgoing port is referred as the address of the shared buffer memory 3 from which the cell being stored is to be read out, and the cell read out from the shared buffer memory 2 is put into the cell slot on the time division multiplex data bus 12 corresponding to the output port.
In the case of an example shown in FIG. 5(c), the address information of "BBB" is read out from the address pointer queue of FIFO 5 for the No. 3 outgoing port, the cell in the shared buffer memory 2 with the address "BBB" is read out and then the cell is put into the cell slot on the time division multiplex data bus 12 corresponding to the No. 3 outgoing port. Also, at the time of reading for the address pointer queue of FIFO 5 for the No. 7 output port, the address information of "MMM" is read out, the cell in the shared buffer memory 2 with the address "MMM" is read out and then the cell is put into the cell slot on the time division multiplex data bus 12 corresponding to the No. 7 outgoing port.
The cell in each of cell slots for the output ports on the time division multiplex data bus 12 is transferred to the cell demultiplexer 7 which demultiplexes cells on the time division multiplex data bus 12 and distributes each cell to the corresponding output port.
As explained above, the ordinary cell coming through one of input ports is switched and output through one of output ports. In the case of the broadcasting (or multicasting) operation which is used for a broadcast application, a multiple connection in desktop conference applications, etc., the cell to be broadcasted coming through one of input ports is switched and output to a plural number of output ports simultaneously.
This broadcasting operation is handled by the address pointer queue for the broadcasting operation shown as FIFO BC of the FIFO memory 5 and the broadcast registration table 6 in FIG. 2, and FIG. 6 shows the outline of the broadcast registration table 6.
The broadcast registration table 6 registers destination output ports for each broadcasting cell in the form of bit map data in which each bit corresponds to each output port, and a bit position set as "1" indicates the destination output port. The bit map data for each broadcasting cell is registered when the connection of the cell is set up and eliminated when the connection of the cell is released. The bit map data for a particular broadcasting cell is indexed and extracted by the routing information based on VPI and VCI in the operation of the shared buffer memory control 2.
The writing operation for the broadcasting cell is similar to that for the ordinary cell, but the reading operation is different. The writing operation and the reading operation for the broadcasting cell will be described in the following with the reference to FIG. 2.
When a broadcasting cell is input through one of input ports, the shared buffer memory control 2 can distinguish that this cell is a broadcasting cell by the routing information transferred from the cell multiplexer 1, and extracts an address of idle area in the shared buffer memory from the FIFO 4 through the information path 16. The shared buffer memory control 2 stores the cell (the broadcasting cell) into the area of the shared buffer memory indicated by the extracted address, and then writes the address into the address pointer queue for the broadcasting control FIFO BC through the information path 17.
In the reading operation for the broadcasting control, the shared buffer memory control 2 reads out the address of the shared buffer memory in which the broadcasting cell is being stored from the address pointer queue FIFO BC through the information path 19. After the broadcasting cell has been read out, the shared buffer memory control 2 then extracts the bit map data corresponding to the cell from the broadcast registration table 6. The shared buffer memory control 2 puts the cell into each cell slot for the output ports in accordance with the bit map data showing the bit positions with "1".
As described above for the conventional shared buffer memory switch and its broadcasting operation, the switch works for the ordinary cells and the broadcasting cells independently, and it is sometimes common for the address pointer queue for the broadcasting cells to have priority in the reading operation and this causes an irregular operation in that the ordinary cell written in the address pointer queue for a specific output port arrived earlier than a broadcasting cell, and is read out later than the broadcasting cell to the same output port. Therefore, the shared buffer memory switch cannot maintain the sequence of outputting cells in the order of arrival of cells, and this causes problems in guarantee of the transfer quality at the same level defined for each connection because ordinary cells and broadcasting cells are output to an output port in a different order even if those cells have the same transfer quality which should guarantee maintaining the sequence of outputting in the order of arrival.